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RSE-FMC-1216ADDA：Dual 12-bit ADC (2.6 GSPS)/ Dual 16-bit DAC (12.6 GSPS) FMC Module (Vita57.1) Based
This daughter card is an FMC board for the high-speed AD9172 DAC and AD9689 ADC. Provides customers with up to 2 GHz of available analog bandwidth and a JESD204B interface to rapidly prototype a wide variety of wideband RF applications.
AD chip AD9689, AD9689-2600EBZ supports AD9689-2600 — 14-bit, 2.6GSPS dual-channel digital-to-analog converter (ADC). The device features on-chip buffers and sample-and-hold circuitry to ensure low power consumption, small package size, and excellent ease of use. The device is specifically designed to support direct RF sampling of analog signals up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD9689 is fully optimized to provide a wide input bandwidth, fast sample rate, excellent linearity, and low power consumption in a small and compact package.
The AD9172 is a high performance dual 16 digital-to-analog converter (DAC) supporting a DAC sampling rate of 12.6 GSPS. The device features an 8-wire 15 Gbps JESD204B data input port, high-performance on-chip DAC clock multiplier, and digital signal processing for single- and multi-band direct-to-radio frequency (RF) wireless applications. The AD9172 features 3 bypassable multiplexed data input channels per RF DAC. Each data input channel includes configurable gain stages, interpolation filters, and channel numerically controlled oscillators (NCOs) for flexible multiband planning. The device supports multiplexed data rates up to 1.5 GSPS per input channel and can aggregate multiple multiplexed input data streams for a maximum multiplexed data rate of up to 1.5 GSPS. Additionally, the AD9172 supports an ultra-wideband mode that bypasses the channel selector to provide maximum data rates up to 3.08 GSPS (16-bit resolution) and 4.1 GSPS (12-bit resolution).
The HMC7044 is a high-performance dual-loop integer divide-by-N jitter attenuator capable of frequency selection and generation of ultra-low phase noise for high-speed data converters with parallel or serial (JESD204B-style) interfaces. The HMC7044 features two SPI-selectable integer-mode PLLs and overlapping on-chip VCOs with tuning ranges up to 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs and simplifies the design of baseband and radio card clock trees through a variety of clock management and distribution features. The HMC7044 provides 14 low-noise and configurable outputs that provide the flexibility to interface with many different devices, including data converters, field programmable gate arrays (FPGAs), and mixer local oscillators (LOs).
Main Features:
Reference Designs/Demos:
Ordering & Availability Information: RSE-FMC-1216ADDA, price: contact us
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